CprE 281/282

Preface

Computer Engineering 281/282 is an introduction to the world of digital logic, processor and computer organization. The laboratory exercises are intended to reinforce your understanding of classroom material with the use of computer as an experimental environment. The computer-aided-design tool we will be using this semester is QUARTUS II.

We will be using an Altera MAX FPGA device, EPM7128SLC84-7, for our exercises. The next section describes the pin layout for the FPGA. Following that is a section describing the pin assignments for the MAX_DIGIT display, which are pre-wired to the FPGA pins. This information will be needed when a design is to be downloaded and tested using the Altera University Program (UP1) Education Board.

EPM7128S Prototyping Headers’ Pin Assignments

The EPM7128S device is located in an 84-pin plastic J-lead chip carrier (PLCC) package. There are a total of 21 pins on each side of this 84-pin PLCC package, which are connected to one of the 22-pin, dual-row 0.1-inch female headers. Since there are only 21 pins on each side of the device, there is an unassigned pin on each side of the connector. The pin numbers for the EPM7128S device are shown as follows:

N

Unconnected pins (unavailable for use)

Reserved pins (not modifiable)

N

JTAG signal pins (unavailable for use)

Unassigned pins.

MAX_DIGIT Display’s Pin Assignments

The dual-digit seven-segment display is pre-wired directly to some of the I/O pins of EPM7128S device. The LED segments of the display are all active LOW, illuminating when driven by a logic 0. The segments of the display are named a, b, c, d, e, f, and g, as shown in the diagram below. The pin assignments are also given in the table below.

Display Segment Names

MAX_DIGIT Segment I/O Connections
Display Segment	Pin for Digit 1	Pin for Digit 2
a	58	69
b	60	70
c	61	73
d	63	74
e	64	76
f	65	75
g	67	77
Decimal Point	68	79

CPR E 281x/282x - Lab 2a

Introduction to Computer-Aided Experimentation

Objectives

Greetings and welcome to the wonderful world of experimental computing. The objectives of this lab session are twofold:

1. To introduce you to the use of the computer as an experimental environment in order to reinforce your understanding of classroom topics.

2. To introduce you, in a gentle way, to one of the computer-aided-design tools we will be using this semester.

Reference Files for the Lab

Lab2aFiles.zip

Lab Evaluation Form

Setup

When you arrive at the lab, you should pair yourself up in a group of two, and find yourself a desktop computer. On the desktop of the computer you should find an icon labeled QuartusII. This is the software we will be using for this lab throughout the semester. Double-click the icon and start the program. If you cannot find the icon, click on Start menu, Program submenu, Altera submenu, and select Quartus II.

You are now ready to proceed with the lab session, which consists of the lab steps given below. Lab questions should be presented on the answer sheet provided to you in the lab handout. Note that corresponding to each lab step is a directory with the same name in your Lab2a folder. When you are to perform a given lab step you are to open the appropriate file using the Quartus II Manager, then answer the questions or perform the required tasks as explained in the lab handout. Upon completion of the step you are to close all the relevant windows.

Create a folder for Lab 2 on your U: drive, download the zip file, and unzip it.

Step1

Part A

You will need to create a new project for Step1a. To do this, select File | New Project Wizard. The working directory for the project should be Lab2Step1a. Browse to it on your U: drive. The name of the project should be lab2step1a. Click here for an example image.

Click next. You will need to add the following files from the Lab2Step1a directory: lab2step1a.bdf, bin2hex.bdf, and 7segment.tdf.

Click next. You will now need to select the device we will be using for the lab this semester. For family select MAX7000S, then under devices choose EPM7128SLC84-7. This is the FPGA device mentioned earlier that we will be using for all labs. Click finish to create your project.

Click on the files tab of the Project Navigator window and expand the Device Design Files folder to view the design files for this project. Double click on lab2step1a.bdf to open the file. Notice that the circuit takes 4 inputs and produces 7 outputs. The function of this circuit is to convert a binary number to a hexadecimal number. Note how inputs are presented to a circuit and how outputs from a circuit are displayed. In general, we will use binary switches on the UP1 Board (MAX_SW1) to represent binary inputs and a seven-segment display on MAX_DIGIT to show the hexadecimal output. You can manipulate the input values by flipping the switches on MAX_SW1.

To compile this design, first right click on lab2step1a.bdf and select Set as Top-level Entity. Then select Processing | start Compilation (or click on the purple arrow icon). A compilation report window should open, and you will see many messages in the bottom window as the design compiles. Pay attention to warning messages. These messages mean that although your design compiled without error, QuartusII has noticed something may be wrong. Sometimes these messages can be ignored. Often times, though, they provide valuable clues if your design is not working correctly.

In order for this design to work, we need to map the pins in the design to pins on the FPGA. This is done by selecting Assignments | Pins. Double click the <<new>> box in the To field and select the node names (example: Fa) then type the assigned number in the Location field. To use the MSB (left) 7-Segment Display we will follow the Pin assignment below.

Outputs	Pin Location
Fa	69
Fb	70
Fc	73
Fd	74
Fe	76
Ff	75
Fg	77

Table 1: 7-Segment Display output pin numbers

And the following pins will be used to grab inputs from the Dip switch.

Inputs	Pin Location
A0	4
A1	6
A2	8
A3	10

Table 2: Input pin numbers

Click here for a screen shot after this step. Re-compile the design when you are finished.

Next, we will be downloading the current design to the ALTERA University Program (UP1) Education Board. Talk to your lab instructor if you do not have a board by now. On the left-top corner of the board, you should see a DC_IN input for power supply. Connect a power adapter to the DC_IN, and you should see the POWER LED light up. The next connector to the right of the DC_IN, is the JTAG_IN connector. Connect the cable that is attached to the parallel port of your CPU to the UP1 Board. Your lab instructor will assist you as necessary.

Now select tools | Programmer from the top menu. The Programmer window will open. If lab2step1a.pof is not shown in the File field of the Programmer window, click the Add File… button and select lab2step1a.pof as your programming file. Check the Program/Configure check box. If you do not see “ByteBlaster” on the top click Hardware Setup and Add Hardware. Choose ByteBlaster in Parallel Port LPT1. NOTE: If you get a JTAG server error, you will need to reboot your computer (not just log off) to restart the JTAG server.

Click on the Start button to start programming the UP1 Board. The TCK LED on the UP1 Board should light up during the programming, and when it goes off, the programming is done. Finish the remaining parts of Step 1a with the programmed UP1 Board.

Experiment with the circuit, lab2step1a, by changing the inputs and observing the outputs. The lab2step1a circuit converts an unsigned 4-bit binary integer into its hexadecimal equivalent. Try the following inputs:

0000, 1000, 0100, 0010, 0001, 1111, 1010, 0110.

Part B

Open the lab2step1b design using the steps similar to lab2step1a. Compile the design and perform pin mapping the pins are the same for A0-A3, and Fa-Fg. For your convenience, you may cut and paste the pin assignments from the following link. Use the following pin mappings for Ga-Gg:

Outputs	Pin Location
Ga	58
Gb	60
Gc	61
Gd	63
Ge	64
Gf	65
Gg	67

Table 3: Second 7-Segment Display output pin numbers

Download the design. The lab1step1b circuit converts an unsigned 4-bit binary integer into its decimal equivalent. Experiment with the following inputs:

0000, 1000, 0100, 0010, 0001, 1111, 1010, 0110.

Step 2

You are given three circuits in Step2. These circuits manipulate 8-bit number. Create a project and download the files as with step 1. Use the link to set the pin assignments. You will set the numbers and observe the outputs:

a) First day of school… do some addition! J Indicate the carry out.

11111111 10000001 11111111 10000000

+00010000 +11111111 +11111001 +11111111

11101111 01010111 11111111 10101110

+11101111 +00111010 +01111111 +10110101

b) Negate the following numbers:

11111111 00000001 10101010 00000000

01010101 11110000 00001111 10000000

c) Subtract the following:

11111111 10000000 01111111 10000000

-00000001 -10000001 -01111111 -11111111

01111111 10000001 01111111 00001101

-11111111 -10000000 -00111111 -00110110

Step 3 - Sign and turn in the lab answer sheet. This completes this lab session.