Carry-Lookahead Adder in Verilog

1. Objectives

In the previous lab you learned how to design modules in Verilog. In this lab you will design a 16-bit carry-lookahead adder. First you will design a CLA unit that will generate carries. Then you will design a 1-bit adder that will produce a generate, sum, and propagate. Then you will build a 4-bit adder using the 1-bit adders, and a 16-bit adder using the 4-bit adders.

1.1 Reference Files for Lab

Lab Evaluation Form

2. Prelab

Before you come to lab it will be useful to become familiar with a carry-lookahead adder. You will find information on the carry-lookahead adder in section 5.4 of your text: “Fundamentals of Digital Logic with Verilog Design” by Brown and Vranesic.

3. Setup

As you did in previous labs, make sure you create the folder in your home directory U:\CPRE281\Lab5a, and then four sub-folders ~\cla, ~\cla_1bit_adder, ~\cla_4bit_adder, and ~\cla_16bit_adder. It is important that you use these folder names. Each module needs to be in its own folder.

4. Design a 1-bit adder

Open a new text editor and write the code for a 1-bit adder with 3 inputs and 3 outputs as shown in figure 1. Name it cla_1bit_adder.v. Use the waveform editor to verify your output. Show the TA your code and waveform results.

5. Design a CLA unit

In the step 6 we will put 4 1-bit adders together with a CLA unit to create a 4-bit carry-lookahead adder. We have the 1-bit adders, so now we need a CLA unit.

The CLA unit generates the carries needed for each of our four adders. It takes the first carry in, and also the propagate and generate outputs from each adder, and uses them to create the carries. So you will need to generate c1-c4 as outputs. Open a new text editor and write the code for the CLA unit shown in figure 2. Name it cla.v. Use the waveform editor to verify your output. Show the TA your code and waveform results.

cla_4bit_adder

6. Design a 4-bit carry-lookahead adder

Open a new text editor and write the code for the 4-bit carry-lookahead adder shown in figure 2. Name it cla_4bit_adder.v. This adder will take a, b, and cin inputs and generate sum, G, P, and Cout outputs. Use the waveform editor to verify your output. Show the TA your code and waveform results.

7. Design a 16-bit carry-lookahead adder

As you can see, the expression for generating 16 carries in your CLA would get quite long. To avoid this we are going to use a hierarchical design for the 16-bit adder by using 4 4-bit adders and one CLA as shown in figure 3. Of course, this will add to the gate delay.

Open a new text editor and write the code for the 16-bit carry-lookahead adder shown in figure 3. Name it cla_16bit_adder.v. This adder is made using 4 4-bit adders and one CLA. Use the waveform editor to verify your output. Show the TA your code and waveform results.