Multiplexers in schematics and Verilog
1. Objectives
In this lab you will design a 2-to-1, a 4-to-1, and an 8-to-1 multiplexer (here after referred to as mux). Each circuit will be designed in both schematics and Verilog. Lastly you will design a full adder using two 8-to-1 multiplexers.
1.1
Reference Files for Lab
2. Prelab
Before you come to lab it will be useful to become familiar with multiplexers. You will find information on multiplexers in section 6.1 of your text: “Fundamentals of Digital Logic with Verilog Design” by Brown and Vranesic.
3. Setup
As you did in previous labs, make sure you create the folder in your home directory U:\CPRE281\Lab5b, and then seven sub-folders ~\mux_2to1_gate, ~\mux_2to1, ~\mux_4to1_gates, ~\mux_4to1, ~\mux_8to1_gates, ~\mux_8to1, and ~\full_adder_mux. It is important that you use these folder names. Each module needs to be in its own folder.
4. Design the multiplexers in schematics
For
each circuit create a new project in the corresponding folder (e.g. ~\mux_2to1_gate for the first circuit). Begin by drawing the circuit to create a
2-to-1 mux. Test it to ensure it’s functioning properly, then create a
symbol for it (refer to lab 4b).
Next,
create a 4-to-1 mux using the 2-to-1 mux you just designed (you will need 3
instances). Test your circuit thoroughly before continuing, as you will
be reusing this component. This also
means you will need to create the symbol for this circuit as well.
Finally use a combination of 4-to-1 muxes and 2-to-1 muxes to create an 8-to-1 mux. You are free to use whatever naming convention you wish for your inputs and outputs. Keep in mind that they should be descriptive and consistent. Test this circuit, remembering to be selective when adding nodes to the waveform editor. When you have verified the waveform is correct, show your TA the schematics for all 3 muxes, and the waveform results for the 8-to-1 mux.
5. Design the multiplexers in Verilog
Again, begin with a 2 to 1, (use the conditional operator (?:)), and then build a 4 to 1, (use if-else statements), and finally build a 8 to 1 mux, (use a combination of the two). Create a project for each one as you go, and don’t forget to copy the .v files you need. Helpful information can be found in section 6.6 of the text. Show the TA all 3 modules and waveform results for the 8-to-1.
6. Design a full adder with multiplexers in schematics
Now that you have a good understanding of how a multiplexer works, let’s put them to use. A simple circuit that can be created using multiplexers is a full adder.
Consider
the truth table for a full adder, which you have undoubted seen over and over:
|
a |
B |
cin |
sum |
cout |
|
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
0 |
1 |
0 |
|
0 |
1 |
1 |
0 |
1 |
|
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
1 |
0 |
1 |
|
1 |
1 |
0 |
0 |
1 |
|
1 |
1 |
1 |
1 |
1 |
There
are many ways to implement this circuit; the method we will be using here is a
look-up table, the very foundation on which FPGA’s are based. Functionally, this method is similar to the
c-program you wrote in an earlier lab.
Recall that in that case we had array holding the values of sum (and one
for cout) from the truth table. The
values of a, b and cin, then were used to select an element from that
array. We will be doing essentially the
same thing, only with hardware instead of software. Instead of two arrays, you will create two
modules, sum_lut.v and carry_lut.v, which will hold the values
from the truth table. Each verilog
module will have no inputs, and one 8 bit output, data_out. The module will have only one line
assigning data_out the values from the truth table (e.g. for sum.v: assign data_out = 8’b10010110). When you compile the modules, you should get
warnings saying the pins are stuck at Vcc or ground, but these are okay. Quartus II is simply informing you that the
values of data_out will never change. After you have compiled, create a symbol
for both modules.
Now
that you have a place where the values are stored, you need to select one from
the 8 choices based on the inputs a, b, and cin. This is precisely the function of the 8-1
mux. Create a new .bdf file for you
adder. Your circuit will have three
inputs (a, b, and cin), and two outputs (sum and cout). Use and instance of the sum_lut and the
carry_lut combined with your 8-to-1 muxes in order to create a full adder. Compile and simulate the circuit to ensure it
is functioning then show your TA.