CPR E 281x/282x - Lab 7a & b
ALU in
Verilog
1. Objectives
You have designed a 16-bit carry-lookahead adder. In this lab, you will
construct a simple version of a 32-bit ALU. First, you are to design a 1-bit ALU
which performs AND, OR, and addition on a and b or b’, then you’ll use the
1-bit ALU to create 4-bit ALU, 16-bit ALU, and 32-bit ALU.
1.1 Reference Files for Lab
2. Prelab
Before
you come to lab it will be useful to become familiar with ALUs. You will find
information on ALUs in section 4.5 of your text: “Computer Organization and Design” by Patterson and Hennessy.
3. Setup
As you did in previous labs, make sure you create the
folder in your home directory U:\CPRE281\Lab7a.
and then four sub-folders ~\cla, ~\alu_1bit, ~\alu_4bit, ~\alu_16bit, and
~\alu_32bit. It is important that you use these folder names. Each module
needs to be in its own folder.
4. 1-bit ALU design in Verilog
To construct a 32-bit ALU which performs AND, OR, and addition on a
and b or b’, you need to
first create a 1-bit ALU. You’ll write
modules from a behavioral point of view. For example, the formula for the carry
out of a 1-bit addition may be written as the following: assign carry_out = (a & b) | ((a | b)
& carry_in). In addition to “assign” statements, you will also use
“always”, “if . . . else”, or “case” statements to build modules.
Each
1-bit ALU takes 1-bit a and 1-bit b input, a carryin input
and produces 1-bit g output, 1-bit p output and 1-bit result.
It also takes 3 control inputs,1-bit binv, and two bits op. binv
inverts the b input bit if binv=1. The ALU should use a carry-in
bit for addition and subtraction. There is an additional input called less
to support set-on-less-than instructions for a complete version of ALU, but in
this lab we’ll ignore this input. We’ll design a complete version later. 2-input bits op selects output as AND
of a and b if they are 00, OR of a and b if they
are 01, SUM of a and b if they are 10, and input less if
they are 11. An additional output called sum is also produced that
always outputs the SUM of a, b, and carryin. The structure of the 1-bit ALU is given below. Create 1-bit
ALU in Verilog. Then run waveform editor and verify your results with
the TA.
Schematic
of 1-bit ALU:
5. 4-bit ALU in Verilog
Create
a 4-bit ALU that is capable of performing addition, subtraction, bit-wise AND,
and bit-wise OR instructions on 4-bit operands. The ALU should use a 1-bit ALU
and carry-lookahead module to perform fast addition and subtraction. First,
draw the block diagram on your answer sheet and check with your TA. Then,
program using verilog in MaxPlusII. You should use your cla module created and
tested in previous labs. Use waveform to verify your results.
6. 16-bit ALU in Verilog
Create a 16-bit ALU that is capable of performing addition, subtraction, bit-wise
AND, and bit-wise OR instructions on 16-bit operands. The ALU should use a
4-bit ALU and carry-lookahead module to perform fast addition and subtraction.
Again, draw the block diagram on your answer sheet first, then program in
verilog. Use waveform to verify your results.
7. 32-bit ALU in Verilog
Create a 32-bit ALU that is capable of performing addition, subtraction, bit-wise
AND, and bit-wise OR instructions on 32-bit operands. The ALU should use a
16-bit ALU and carry-lookahead module to perform fast addition and subtraction.
Use waveform to verify your results.