CPR E 281x/282x - Lab 8b
1. Objectives
In this lab
you will design a 4x4bit Register File and a 16x16bit Register File.
1.1
Reference Files for Lab
2. Prelab
Before you
come to lab it will be useful to become familiar with the concept of register
files. You will find information in
Chapter 7 of your text “Fundamentals of
Digital Logic with Verilog Design” by Brown and Vranesic.
3. 4x4bit Register File (structural
design)
A register file is a key part of a microprocessor. It consists of a set of registers, each of
which can be read from or written to. These
registers are used to store values that the processor is working on. For example, when calculating a+b = c, the
values for a, b, and eventually c would all be stored in the registerfile of
the microprocessor.
We will start by designing a 4x4bit register file, registerfile4x4
(datain, dataout1, dataout2, addra, addrb, addrc, write, clock), that will contain 4 registers, each 4 bits
wide. Write the verilog code given the
description below.
Inputs:
[3:0]
datain
[1:0]
addra, addrb, addrc
write, clock
Outputs:
[3:0] dataout1, dataout2
Behavior:
The registerfile must be capable
of two simultaneous register reads. The
inputs addra and addrb will be used to select which
register will show up on the outputs dataout1
and dataout2 respectively. For example, if addra is 00 and addrb is
10, then dataout1 should display the
value in register0, and dataout2
should display the value in register 2.
These outputs should be enabled at all times, that is to say, the value
of dataout1 (and 2) will change whenever addra (or addrb) changes, or when the
value in the selected register changes.
In addition, one register may be
written into every clock edge. The input
addrc will select which register is
written to. The new value of the
register is given by datain, which
will be written to the selected register at the rising edge of clock only if the value of write is 1. If the write
signal is a 0, no registers should be written to.
Your design should consist of four 4bit registers designed in the previous lab, one 2-to-4 decoder with enable, and two 4-to-1 multiplexers (each 4-bits
wide). First draw the schematic in the
space provided on the answer sheet, then program the design in Verilog. Test the design with this waveform to ensure is it working correctly.
4. 16x16bit Register File
(behavioral design)
You have just designed a 4x4bit registerfile using a
structural method (i.e. we broke the design down into components, created
instances of the components, and connected them together with wires). We now need to make a larger register file,
16x16bits. However, with a design this
large, the structural method will not work, because it does not allow the Quartus
II to adequately optimize the design. In
order to allow this to occur, we must use a higher level of design. At the behavioral level, constructs similar
to c are used to describe the behavior of the module. Using a case statement to create a 2-to-4
decoder is an example of a behavioral design.
Write the verilog code for a 16x16bit registerfile, registerfile
(datain, dataout1, dataout2, addra, addrb, addrc, write, clock). The inputs and outputs will be the same, but
you will have to modify the bit-widths as appropriate. The performance will be exactly the same as
for the 4x4bit, except the writes should be negative edge triggered,
i.e. writes will occur at the negative edge of the clock. Use behavioral level techniques such as always blocks and case statements. Here are a
few hints to get you started:
Hints:
reg
[15:0] regs [15:0]; // where the first
[15:0] specifies the width of each register, regs is the name of the array, and
the second [15:0] is the number of registers
always
@(negedge clock)
begin
…
When you are done, use this waveform to test your design and show your TA your
results.