CPR E 281x/282x - Lab 13a
Designing
Registers and Counters
The objective is to learn the functioning of shift
registers and counters. You will design the shift-registers and counters and
see them function. You will be using Schematic Capture for this lab.
1.1 Reference Files for Lab
1. Prelab
Review Chapter 7.8 and 7.9 in your Brown and Vranesic
textbook before performing the laboratory.
2. Design Steps
A shift register is a specialized register that takes
an input serially and shifts it from bit position to bit position. A full explanation of shift registers is
available in Chapter 7.8 of the Brown and Vranesic text. Figure 7.18a shows a
four-bit shift register built using D Flip-Flops.
For this step in the lab you will use the D flip-flop
of the LPM Library to build a shift register. Open a new .bdf file and name it lab13astep1.bdf. Set this file to the top level entity. Right
click on the BDF file and do an Insert |
Symbol…. In the libraries dialog Box choose “c:\program files\altera\quartus50\libraries\primitives\storage”
for the symbol library. Then you can choose the “dff” symbol file to get a D
Flip-Flop (Alternately, type dff in the name:
field). Set the preset and the clear inputs of this flip-flop to high (connect
to vcc).
You need to design a 4-bit shift register using the D
Flip-Flops. Use the figure 7.18(a) as a reference. You are to compile the file,
use the waveform editor to prepare the file for simulation, and then simulate
the design using the simulator. Does the output change after the rising clock
edge? If not, review how a positive-edge triggered device responds and
propagation delays associated with D flip-flops. When you are convinced your
design is working correctly, verify your observations and design with your TA.
You can use the same flip-flop design from Step 1 to
create counters. Counters are either synchronous (common clock signal) or
asynchronous. A discussion of
synchronous counters may be found in Chapter 7.9.2 of your textbook. Figure
7.24 describes how a 4-bit counter can be built using D Flip-Flops.
Open a new .bdf file and name it lab13astep2a. Use the D Flip-Flops (As in Step1) and additional
gates to build a synchronous 4-Bit Up-Counter. Use the Figure 7.24 in your text
as a reference.
Simulate the circuit and necessary inputs, and
observe the behavior of this counter.
When you are confident you understand the behavior of this device, and
are convinced it is performing as predicted, show your work to your TA.
Open a new .bdf file and name it lab13astep2b. Use T Flip-Flops and additional gates to build a
synchronous 4-Bit Up-Counter. Use the Figure 7.22(a) in your text as a
reference. You can get T Flip-Flops from the LPM prim library the way you got
the D Flip-Flops. To get a T Flip-Flop you need to select the “tff” symbol
file. Set the preset and the clear inputs of this flip-flop to high.
Simulate the circuit and necessary inputs, and
observe the behavior of this counter.
When you are confident you understand the behavior of this device, and
are convinced it is performing as predicted, show your work to your TA.
For Step 3 you will build two designs for
asynchronous counters. Async counters
can be built using T flip-flops.
In the first part of this step, you will build a
4-bit asynchronous up-counter. The figure 7.20(a) shows a 3-bit async
up-counter using T Flip-Flops. Extend this circuit to build a 4-bit async
up-counter. Use the T Flip-Flops from the LPM library the way you did in Step
2.
Use the waveform editor to simulate the 4-bit
up-counter circuit with a single T input value of 1. Simulate the design and
determine the propagation delay for this circuit. Satisfy yourself that design
is working properly. What is the
propagation delay for this circuit?
Verify with your TA.
For Step 3b, you will build a 4-bit asynchronous down-counter
using T Flip-Flops. The figure 7.21(a) shows a 3-bit async down-counter using T
Flip-Flops. Extend this circuit to build a 4-bit async down-counter. Use the T
Flip-Flops from the LPM library the way you did in Step 2.
Use the waveform editor to simulate the circuit with
a single T input value of 1. Simulate
the design and determine the propagation delay for this circuit. Satisfy yourself that design is working
properly. What is the propagation delay
for this circuit? Verify with your TA.
Close your files.