Cpre305 Homework #5

Reading Assignment: Chapter 4-1-4.6.

P1. (10 points) Problem 4.40.

P2. (10 points) Problem 4.42.

P3. (10 points) Problem 4.45.

P4. (10 points) Problem 4.48.

P5. (10 points) Problem 4.49

P6. (10 points) Problem 4.51.

Lab HWs (to be done by hand only, but if you want you may run them on MAX Plus II.

P7. (10 points) Design a 4-function 1-bit ALU (as shown in book Figure 4.17, top) using Verilog. Submit your code.

P8. (10 points) We will now improve the design of the 4-function 1-bit ALU. Design a carry look module, CLA (g0.g1,g2.g3,p0,p1,p2,p3,cin,G,P,C0,C1,C2,C3,C4), that takes 4 generate (g's) and 4 propagate (p's) terms and a carry input (cin) to produce a block generate (G), a block propagate (P), and five output carries (C0-C5). Also, change your 1-bit ALU block to accept carry as input and not to produce an output carry. Instead, it should produce the g-term (AND) and the p-term (OR) as additional outputs.

P9. (10 points) Modify the one_bit_ALU design and CLA design to include gate delays. Each gate has one gate delay. A mux will have two gate delays. Modify the test module to test this module out. Submit the modified modules and test module. What are the delays through the one_bit_ALU and CLA modules?