Cpre305 Homework #7
Reading Assignment: Section 5.1 - 5.3 and start reading Section 54..
P1. (10 points) Problem 5.1
P2. (10 points) Problem 5.9 (repeat)
P3. (10 points) Problem 5.12
P4. (10 points) Problem 5.13
P5. (10 points) Problem 5.14 (repeat)
P6. (50 points) (Verilog Problem) Thus far we have been designing using
structural model and getting in problems of largeness). However, that
provided us the understanding of what goes on in a register file and in
an ALU. We will switch gears and design using a register transfer behavior
model. We will develop several modules at the behavior level in this problem.
1. Design a register file consisting of 32 registers, 32 bits each, named
REG_FILE(ADDA, OUTDA, ADDB, OUTDB, ADDC, IND, WE, CLK).
ADDA and ADDB are two 5-bit addresses to read two registers simultaneously.
The two 32-bit data sets are available on ports OUTDA and OUTDB, respectively.
OUTDA and OUTDB are registered output (output of register file is written
into these registers at the falling edge of the clock). You can view it as
if outputs of registers specified by ADDA and ADDB are written into output
registers OUTA and OUTB at the falling edge of the clock. (Note: We will design
register file (in real hardware) such that the contents of registers do not
change for a pre-specified time before the falling edge of the clock arrives
to allow for data multiplexing and setup time.)
ADDC is a 5-bit address of the register to be written. IND is a 32-bit
input data port specifying the data to be written into the specified register.
WE signal is high during the rising edge of the clock if the input data is to be
written into the register file. The contents of register
specified by address ADDC in the register file are modified at the rising edge of the clock if WE signal is high. The D-flip flops in the register file
are positive-edge (rising-edge) triggered. (You have to use this information
to generate the write-clock properly.)
CLK
is the free-running clock signal with a high time of 1 unit and low time of 3
units.
Write a test module, TEST_REG_FILE to test the register file. It has 2
multi-bit inputs, a 32-bit IR and a 32-bit IND, and two single bit input WE and
CLK. It produces two 32-bit outputs that are same as the output of register
files, namely OUTDA and OUTDB. ADDA and ADDB are bits 25-21 and 20-16 of IR.
Bits 15-11 of IR supply ADDC. IND, WE, and CLK directly provide the
corresponding signals for the register file. Choose
a few test cases and submit your simulation output along with the code
for REG_FILE and TEST_REG_FILE.
2. Design a 32-bit 4-function ALU, named
ALU(PORT1, PORT2, SEPORT, ALUCON, ALUSEL, ALUOUT, CLK).
The four functions perform operation on two 32-bit operands, and are AND, OR,
ADD or SUB under the control of another input, and SLT (set 32-bit output
to value one or zero depending on if the first operand is smaller than
the second operand or not, respectively). PORT1, PORT2, and SEPORT are
three 32-bit inputs. PORT1 is a 32-bit input to be used as the first of
the two 32-bits operands to the ALU. ALUSEL is a control signal specifying
which one of the two inputs namely PORT2 or SEPORT should be used
as the second operand to the ALU. ALUCON is a 3-bit control sequence. Bit
2 of ALUCON is used to specify if the ALU should perform an ADD or
SUB operation. The four combinations of Bits 1 and 0 are used to specify
the function as follows: 00 for AND, 01 for OR, 10 for ADD/SUB, and 11 for SLT. ALUOUT
is the output of the selected function.
CLK
is the free-running clock signal with a high time of 1 unit and low time of 3
units.
Test the module assuming that the three inputs, PORT1, PORT2, and SEPORT,
are specified as part of three registers, OUTDA, OUTDB, and SEIR, respectively.
ALUSEL and ALUCON are specified as 1-bit and 3-bit registers. Choose
a few test cases and submit your simulation output along with the code
for ALUand TEST_ALU.