Cpre305 Homework #9

Reading Assignment: Chapter 6.

P1. (10 points) Problem 6.3
P2. (10 points) Problem 6.4.
P3. (10 points) Problem 6.5.
P4. (10 points) Problem 6.7.
P5. (20 points) Problem 6.10.
P6. (10 points) Problem 6.19.

Verilog Problem (30 points) Develop a stand-alone instruction fetch unit. It consist of a PC register and a memory unit and logic to increment the address by four.

FETCH (IR, PCOUT, PCIN, WEPC, INHINC, CLK).

Every clock cycle it takes the address of an instruction from PC register, fetches the 32-bit instruction from memory and deposits in a register called IR. It also increments the address used to fetch the instruction by four and stores it in PC if INHINC signal is not active (it must not be logic 1). PCOUT is the value of address used to fetch the instruction incremented by four. PC is set to a new value specified by PCIN instead of incremented value if WEPC signal is active (logic 1). CLK is a free running clock. All registers are loaded at the rising edge of the clock.