CprE 305

Lab 02 - Translating from Gate-Level Design to Verilog

The focus of this lab is on becoming more familiar with verilog, as well as the Max PlusII simulation tools.

1. Make sure you are familiar with Verilog and the MaxPlusII Simulator Environment by looking over the tutorials for both:
   Verilog
   Simulator
2. The following is a diagram for a 4-2 priority encoder, with the ina0 line removed (since it has no effect on the output). Construct a truth table for the schematic.

   

3. Using verilog, construct the encoder. Verify the results you received from your truth table by simulating your circuit. Your simulation should be very easy to read, similar to the style used when constructing truth tables.
4. Show your TA the truth table, your verilog code and your verified simulation results.