Lab 5

CprE 305

In lab 4, you designed a 16-bit ripple-carry adder. When you ran the simulation, you should have noticed that the result sometimes required a long time to “settle” to the correct value. Addition is a common operation, and a principle of computer architecture is to make the common case fast. In this lab, you’ll design a faster adder.

1. Design a 4-bit carry look-ahead block that takes four g-inputs (g0-g3), four p-inputs (p0-p3) and one carry input cin. It produces five carryout bits (c0-c4) and a block Generate (G) and a block propagate (P) outputs. Equations for the outputs are given in your textbook. Call this block as CLA

2. Develop a three-level hierarchy to implement a 16 bit fast adder. In the first level we have 16 adder 1-bit adder blocks. Each 1-bit adder generates three outputs, g, p, and s, and takes three inputs, a, b, and cin. In the second and the third level of hierarchy we use 4 bit CLA block designed in step 1.

3. Your design should provide a result in only 8 gate delays, not the 32 gate delays that are needed by a 16-bit ripple-carry adder.

4. Extend your design to implement a 32-bit adder. Determine how many levels you need to implement?

· As in the ripple-carry adder, you should use a hierarchical design for the carry-look-ahead adder.

· You should put comment lines in your code, so that both you and your TA do not get lost in the code of long modules.