Lab 8

CprE 305

In this lab, we will combine the four-bit register with the four-bit ALU for a single-cycle implementation without memory. We will execute the following instructions (in the given order):

add $r3 $r1 $r2

sub $r2 $r3 $r0

or $r0 $r1 $r2

and $r3 $r2 $r1

slt $r2 $r1 $r0

Remember that the first input is the “result” and the second and third inputs are the two operands. Therefore, the slt instruction will put a value of 1 into r2 if (r1) < (r0).

Thus far we have been designing using structural model and getting in problems of largeness). However, that provided us the understanding of what goes on in a register file and in an ALU. We will switch gears and design using a register transfer behavior model. We will develop several modules at the behavior level in this problem.

1. Design a register file consisting of 4 registers, 4 bits each, named

REG_FILE(ADDA, OUTDA, ADDB, OUTDB, ADDC, IND, WE, CLK).

ADDA and ADDB are two 2-bit addresses to read two registers simultaneously. The two 4-bit data sets are available on ports OUTDA and OUTDB, respectively. OUTDA and OUTDB are registered output (output of register file is written into these registers at the falling edge of the clock). You can view it as if outputs of registers specified by ADDA and ADDB are written into output registers OUTA and OUTB at the rising edge of the clock. (Note: We will design register file (in real hardware) such that the contents of registers do not change for a pre-specified time before the rising edge of the clock arrives to allow for data multiplexing and setup time. )

ADDC is a 2-bit address of the register to be written. IND is a 4-bit input data port specifying the data to be written into the specified register. WE signal is high during the rising edge of the clock if the input data is to be written into the register file. The contents of register specified by address ADDC in the register file are modified at the rising edge of the clock if WE signal is high. The D-flip flops in the register file are positive-edge (rising-edge) triggered.

CLK is the free-running clock signal with a high time of 1 unit and low time of 3 units.

Write a test module, TEST_REG_FILE to test the register file. It has 2 multi-bit inputs, a 9-bit IR and a 4-bit IND, and two single bit input WE and CLK. It produces two 4-bit outputs that are same as the output of register files, namely OUTDA and OUTDB. ADDA and ADDB are bits 1-0 and 3-2 of IR. Bits 5-4 of IR supply ADDC. IND, CLK, and WE directly provide the corresponding signals for the register file. Choose test cases.

2. Design a 4-bit 4-function ALU, named

ALU(PORT1, PORT2, SEPORT, ALUCON, ALUSEL, ALUOUT, CLK).

The four functions perform operation on two 4-bit operands, and are AND, OR, ADD or SUB under the control of another input, and SLT (set 4-bit output to value one or zero depending on if the first operand is smaller than the second operand or not, respectively). PORT1, PORT2, and SEPORT are three 4-bit inputs. PORT1 is a 4-bit input to be used as the first of the two 4-bits operands to the ALU. ALUSEL is a control signal specifying which one of the two inputs namely PORT2 or SEPORT should be used as the second operand to the ALU. ALUCON is a 3-bit control sequence. Bit 2 of ALUCON is used to specify if the ALU should perform an ADD or SUB operation. The four combinations of Bits 1 and 0 are used to specify the function as follows: 00 for AND, 01 for OR, 10 for ADD/SUB, and 11 for SLT. ALUOUT is the output of the selected function.

CLK is the free-running clock signal with a high time of 1 unit and low time of 3 units.

Test the module assuming that the three inputs, PORT1, PORT2, and SEPORT, are specified as part of three 4-bit registers, OUTDA, OUTDB, and SEIR, respectively. ALUSEL and ALUCON are specified as 1-bit and 3-bit registers. Choose test cases.

Now we will connect ALU to register file. We will assume that instructions are encoded in 9 bits, top 3 bits are opcode (specifying ALUCON bit for the instruction), next two bits are ADDA (for operand 1), next two bits are ADDB (for operand 2), and the last two bits are ADDC. Connect OUTDA to PORT1, OUTDB to PORT2, ALUOUT to IND, 0000 to SEPORT, IR bits properly to ADDA, ADDB, ADDC, and ALUCON. ALUSEL should be always 0.

Initialize registers r0, r1, and r2 in register file with the values 1, 3, and 2, respectively.

Generate the bit streams as per the given instruction sequence and see that you are able to execute the instructions correctly.