Lab 9

CprE 305

In this lab, we will create a memory module, MEM (ADDIN, DATAOUT, CLK, DATAWRITE, RE, WE). Since Max +plus II does not support memory statements (i.e. reg [3:0] inst [8:0]), you will need to use lots of variables (mem00, mem04, …., mem60, and a long case statements.

a. ADDIN is the address input. It is a 6-bit value, capable of referencing 16 data words that are located at address 0, 4, 8…... , 60.

b. DATAOUT is the output of memory (memory contents). For this lab, data will be k-bits wide. We will use two values of k, i.e. k=9 for inst memory and k=4 for data memory.

c. DATAWRITE is the k-bits data that is to be stored into the memory.

d. CLK, RE, and WE are the clock, read enable, and write enable inputs. You should write into the memory at the positive edge of the clock only if WE signal is active. If RE is not active, then DATAOUT should be undefined.

1. Using the above module, create two modules, one for instruction (IMEM) and one for data memory (DMEM).

2. Create a PCSET module, PCSET (BRANCH, INITPC, OUTPC). This module will be responsible for incrementing the PC by 4 (to read the next instruction). Within the module, you should also use BRANCH within a condition statement to set the PC value to either the (PC + 4) or the branch address that will be available externally depending on if the BRANCH signal is 0 or 1. INITPC is the branch address) or initial PC value), and OUTPC is the 6-bit PC output. See page 452 in the book for a picture of this setup.

3. Create a module, called IFETCH, that calls use both IMEM and PCSET. Initialize instructions 5 and 11 with the following two 9-bit instructions:

sub $r3 $r2 $r1 (bit pattern 110 11 10 01)

or $r2 $r0 $r1 (bit pattern 001 10 00 01)

Read each instruction sequentially until you can show instructions 5 and 15 (and yes 15 not 11) as the output of the IFETCH module. Use the waveform generator to do this and show your TA the output.