Lab 11

CprE 305

 

In this lab, we will design a control unit for a processor with a multi-cycle datapath. The instructions supported by this processor are listed in the table below.

R-format	add, sub, and, or, slt
I-format	addi, andi, ori
Memory	lw, sw
Branch	beq, bne
Jump	j, jal, jr

 

For more information about the instructions in the table, refer to appendix A (p. A-53).

 

The control unit will be implemented via a finite state machine, similar to the one in section 5.4.

 

First you need to determine if the datapath shown on page 383 supports all the required instructions. If not, you need to modify it and add the necessary control signals. (Use the same control signals as those in the diagram on page 383)

 

Draw a state diagram of the state machine and show it to your TA.

Then implement the state machine in Verilog, test at least one instruction from every group and show the resulting waveform to your TA.