Dated: Modified October 20, 2003
VERILOG TEST MODULE: YOU HAVE BEEN TESTING VERILOG USING WAVEFORM. YOU CAN ALSO TEST YOUR MODULES USING TEXT DESCRIPTION OF TESTS (THAT IS ANOTHER WAY TO REPRESENT WAVEFORMS). I HAVE ADDED TWO EXAMPLES UNDER "SOME VERILOG MODELS", i.e. ALU AND ITS TEST. YOU SHOULD USE THEM TO ANSWER QUESTIONS FOR TOMORROW HOMEWORK.
YOU DO NOT HAVE TO GIVE A CODE THAT HAS BEEN TESTED IN LAB. YOU CAN GIVE ME HAND WRITTEN CODE FOR HW AND THEN YOU WILL BE DOING THIS IN LAB AS PART OF LAB.
ALSO NOTE THAT MAX PLUS II DOES NOT SUPPORT FULL VERILOG. SO THE SOLUTIONS YOU FIND ON WEB WILL NOT WORK ALWAYS. I AM GLAD THAT YOU ARE ABLE TO FIND SOLUTIONS THOUGH.
Dated: Modified October 16, 2003
Recitation: M 12-1, W 2-3, F 2-3 in room Coover 1201.
Dated: Modified October 13, 2003
From now on you will have the full week to finish the lab. You can finish and show any time during the week to TA. If you do not finish on the day of your lab, make an arrangement with your TA when (s)he can see your solution.
Dated: Modified October 10, 2003
I noticed that about 1/3rd of the class was absent today. I would be taking attendance when I am covering an important transition point in class. Although I do not insist on attendance, I will be taking that in account as I see it fit.