Read the two papers on "making a case for reconfigurable computing" and "comparing computing machines."
P1. Consider the dedicated carry logic of Xilinx XC4000 series.
(a) Show the configurations for F and G LUTs for the following functions implemented with the dedicated carry logic: addition, subtraction, increment by one, decrement by one, 2's complement. Argue why different rows of the F and G LUTs need to be used for addition and subtraction {\it sum} bits in the current carry logic in Xilinx XC4000.
(b) Modify the block diagrams in Figure 1 and Figure 4 of the Xilinx application note \#013 (accessible from the course homepage) so that a single configuration in F and G LUTs can be used for addition and subtraction.
(c) How many rows of the F LUT are needed to compute the add/subtract operation in your revised scheme from Part (b)? Can you reduce it any further by modifying the dedicated carry logic? If yes, give the details, if no, argue why not.
(d) What other addition like operations can be supported by a single F, G LUT configuration by using the rows not used by add/subtract? Maximize the F, G LUT utilization while supporting as many arithmetic operations as possible.
P2. Consider the code for convultion algorithm.
for i = 1 to NumberofIN
{
Y[i] = 0;
for j = 1 to NumberofTAPS
Y[i] += X[i+j-1]*W[j];
}
Design a circuit to carry out the computation for NumberofIN=16 and NumberofTAPS=2. Layout this circuit using Altera or Xilinx tools in room Coover 1318. It is recommened that you start practicing using these tools as soon as possible.
Map the design on any available FPGA and report on statistics
of mapping, in particular number of CLBs utilized, I/O pads etcs.
Understand the reports generated. You can assume that Weights W[]
are constatnts, and thefore use multiplication by constatnt
algorithm. X[] variables are to be pipelined through the circuit.
It may be a good idea to do the computation by hand to figure out
how to pipe data through the circuit.