------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- -- -- File Name: TB_Network_Detection.vhd -- -- Author: Phillip Jones (phjones@iastate.edu ) -- -- Date: 2/1/2018 -- -- -- -- Description: Base testbench for generating stimulus input for -- -- DUT (Device Under Test) -- -- -- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TB_Network_Detection is port ( my_in : in std_logic -- input needed to keep modelsim from complainning??? ); end TB_Network_Detection; architecture rtl of TB_Network_Detection is ---------------------------------------------- -- Component declarations -- ---------------------------------------------- -- Device under test component Network_Detection port ( sysclk : in std_logic; -- system clock reset : in std_logic; -- reset registers and coutners sop : in std_logic; -- indicate start of a packet data : in std_logic_vector(7 downto 0); -- Packet data valid_data : in std_logic; -- Indicate packet data is valid alert_cnt_out : out std_logic_vector(7 downto 0) -- Number of alerts ); end component Network_Detection; ---------------------------------------------- -- Signal declarations -- ---------------------------------------------- -- Make sure to add addtional states here!! type my_input_states is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, STOP_TEST); signal dut1_inputs : std_logic_vector(7 downto 0); -- inputs to dut 1 signal dut2_inputs : std_logic_vector(7 downto 0); signal dut1_outputs : std_logic_vector(7 downto 0); -- outputs from dut 1 signal dut2_outputs : std_logic_vector(7 downto 0); signal input_state : my_input_states; -- Direct which input vector to use signal HOLD_INPUT_reg : std_logic_vector(11 downto 0); -- # clks to hold input signal input_timer : std_logic_vector(11 downto 0); -- timer signal clk : std_logic; signal reset : std_logic; begin -- Processes ------------------------------------------- ------------------------------------------- -- Process Name: system_clk_gen -- -- -- -- Description: Generat clock to run the -- -- simulation. -- -- -- -- -- ------------------------------------------- ------------------------------------------- system_clk_gen : process -- 500 MHz clock begin clk <= '0'; wait for 10 ns; loop wait for 1 ns; clk <= '1'; wait for 1 ns; clk <= '0'; end loop; end process system_clk_gen; ------------------------------------------- ------------------------------------------- -- Process Name: toggle_reset -- -- -- -- Description: Toggle system reset. -- -- used if DUT requires a reset signal -- -- -- -- -- ------------------------------------------- ------------------------------------------- toggle_reset : process begin reset <= '1'; -- place circuit in reset wait for 95 ns; reset <= '0'; wait; end process toggle_reset; ------------------------------------------------------------ ------------------------------------------------------------ -- -- -- Process Name: DUT stimulus -- -- -- -- Send inputs to dut. Holds inputs for HOLD_INPUT_reg -- -- clk cycles -- -- -- ------------------------------------------------------------ ------------------------------------------------------------ DUT_stimulus : process(clk) begin if (clk = '1' and clk'event) then -- Initialize the test if(reset = '1') then input_state <= S0; dut1_inputs <= (others => '0'); HOLD_INPUT_reg <= x"001"; input_timer <= (others => '0'); else -- Cycle thought DUT input stimulus patteren case input_state is when S0 => dut1_inputs <= "00000000"; -- Define what input to give to the DUT input_timer <= input_timer + 1; -- Check if it is time to change the input to the DUT if(input_timer = HOLD_INPUT_reg) then input_timer <= (others => '0'); -- reset timer HOLD_INPUT_reg <= x"00A"; -- Set how many clks to hold the next input input_state <= S1; end if; when S1 => dut1_inputs <= "00000001"; -- Define what input to give to the DUT input_timer <= input_timer + 1; -- Check if it is time to change the input to the DUT if(input_timer = HOLD_INPUT_reg) then input_timer <= (others => '0'); -- reset timer HOLD_INPUT_reg <= x"00A"; -- Set how many clks to hold the next input input_state <= S2; end if; when S2 => dut1_inputs <= "00000010"; -- Define what input to give to the DUT input_timer <= input_timer + 1; -- Check if it is time to change the input to the DUT if(input_timer = HOLD_INPUT_reg) then input_timer <= (others => '0'); -- reset timer HOLD_INPUT_reg <= x"00A"; -- Set how many clks to hold the next input input_state <= S3; end if; when S3 => dut1_inputs <= "00000010"; -- Define what input to give to the DUT input_timer <= input_timer + 1; -- Check if it is time to change the input to the DUT if(input_timer = HOLD_INPUT_reg) then input_timer <= (others => '0'); -- reset timer HOLD_INPUT_reg <= x"00A"; -- Set how many clks to hold the next input input_state <= S4; end if; when S4 => dut1_inputs <= "00000011"; -- Define what input to give to the DUT input_timer <= input_timer + 1; -- Check if it is time to change the input to the DUT if(input_timer = HOLD_INPUT_reg) then input_timer <= (others => '0'); -- reset timer HOLD_INPUT_reg <= x"00A"; -- Set how many clks to hold the next input input_state <= STOP_TEST; end if; when STOP_TEST => input_state <= STOP_TEST; when OTHERS => input_state <= STOP_TEST; end case; end if; end if; end process DUT_stimulus; -- Combinational assignments -- none -- Connect DUT (Network Detection circuit) to the testbench my_dut : Network_Detection port map ( sysclk => clk, -- system clock reset => reset, -- reset registers and coutners sop => dut1_inputs(0), -- indicate start of a packet data => dut2_inputs, -- Packet data valid_data => dut1_inputs(1), -- Indicate packet data is valid alert_cnt_out => dut1_outputs -- Number of alerts ); end rtl;