EE/CprE 501: Analog Integrated Circuit Design

 

Instructor Contact information:

Degang Chen:            2134 Coover Hall

Office Hour:               12:00 - 2:00 pm MWF, or any other time that is convenient to you

Phone:                         294-6277; 294-8432(fax);

E-mail:                         djchen@iastate.edu

Please include "EE501" in the subject line in all email communications to avoid junk-filtering

Teaching Assistant:   

Yulong Shi:                 3102 Coover Hall

Voice phone:               701 306 5095,

E-mail:                         yulong@iastate.edu

Lab Webpage:             http://home.engineering.iastate.edu/~yulong/EE501lab/

Current Semester Assignments:

HW#1; HW#2;

Lab 0; Cadence analog design environment user guide 2006; Cadence wave scan user guide

Current Semester Lecture Notes and supplemental materials:

·         Lecture1: Course Admin; Intro to Analog IC and CMOS process

·         Lecture2: CMOS Technology

·         Lecture3: CMOS Devices

·         Lecture4: CMOS Transistor Models; BSIM4.6.4 Manual; BSIM4.6.5 Bugfix;

·         http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ami-c5/v05q_c5n_non_epi-params.txt

·         Lecture5 CMOS amp; diff amp

·         CG and output amplifiers; Current Mirrors

·         Common mode feedback

·         Compensation;

·         Layout

·         Reference

·         Lowvoltage

·          

·         Lecture on compensation;

·         Layout

·         Lecture on References

·         Lecture on bandgap

·         Lecture on low voltage; Monticelli; Huijsing; Huijsing1; Harrison; Sanchez;

·         Lecture on CMOS process steps, sources of errors,

·         Lecture on CMOS Devices, their layout, process variations

·         Lecture on device model, parasitics, voltage and temperature dependent errors

·         Lecture on Sub-Circuits

·         Kumar’s Final Oral Exam Presentation

·         Kumar’s MS thesis

·         midterm

·         Mason’s Gain Formula for finding transfer functions

Current Semester Project Assignments:

·         Project 1; slides; sample report;

·         Project 2;

Catalog Description

E E 501. Analog and Mixed-Signal VLSI Circuit Design Techniques. (Cross-listed with Cpr E). (3-3) Cr. 4. F. Prereq: 435. Design techniques for analog and mixed-signal VLSI circuits. Amplifiers; operational amplifiers, transconductance amplifiers, finite gain amplifiers and current amplifiers. Linear building blocks; differential amplifiers, current mirrors, references, cascading and buffering. Performance characterization of linear integrated circuits; offset, noise, sensitivity and stability. Layout considerations, simulation, yield and modeling for high-performance linear integrated circuits.

Course Objectives

Understand fundamental concepts related to sources of non-idealities, matching, noise, nonlinearities, and stability.

Design and analyze key building blocks.

Design and analyze multistage op amps for low voltage, low power, high gain, and high speed applications.

Experience floor planning, analog layout, corner simulation, yield assessment, design for test, and test planning.

Prerequisite courses and prerequisite topics

The official prerequisite course for EE501 is EE435, which has EE 330, 324, 330, 332, and either EE 322 or Stat 330 as prerequisite.

In terms of topical contents, the prerequisite for EE501 includes, ranking from the most important:

         Proficiency and fluency in using Cadence, Synopsis, and other IC design and simulation tools

         Knowledge of basic amplifier structures, their large signal and small signal analysis, and computation of their gain, bandwidth, impedance and so on.

         Knowledge of how transistors work, including various operation regions, large and small signal models, and parasitics models.

         Knowledge of signals and systems, including poles, zeros, transfer functions, frequency response, transient response, stability, phase margin, and so on.

         Knowledge of semiconductor fabrication processes and how transistors, resistors, capacitors, diodes, etc., are made.

         Knowledge of probability, random variables, pdf’s, noise, signal to noise ratio, noise transfer, and so on.

Course Coverage and Topics

There are

Evaluation components and weighting in final grades

There are three ways to earn an “A” for the course:

1)      Produce original research results that I deem as publishable or patentable work. If at the end of the semester I don’t think so but later you improve the results and get your paper accepted by a major conference or an acceptable journal, I can go back and change your grade to an “A”.

2)      Achieve “A” level performance in both project specifications, both project reports, and both project presentations. If you decide to take advantage of the free fabrication privilege and your fabricated projects meet or exceed all specifications, then I can go back and change your grade to an “A” based on your updated/improved project reports that have also incorporated the fabrication and measurement results. This is in addition to the extra credit(s) that you will receive for your special topics class for the Spring.

3)      Achieve “A” level performance according to the regular evaluation matrix defined below.

Final Grade Weighting

         Laboratory: 25%

         Design projects: 20% each

         Homework: 15%

         Two Exams: 10% each

         Bonus for

        Classroom participation: 5%

Final Grade Scale:

         A: 95%+

         A-: 90 – 95%

         B+: 85 – 90%

         B: 80 – 85%

         B-: 75 – 80%

         NR: <75%

Other policies

Teamwork, collaboration, and helping each other:

For tasks intended for group work, you are expected to find a partner and share the tasks among the group members. In a group project, effective teamwork is critical to maximize the productivity of the whole group. In the submitted work, identify components and indicate percentage contribution by each member to each component.

For tasks not intended for group work, individual submission is required. In this case, you are encouraged to discuss among your friends on how to attack problems. However, you should write your own solution. Copying other people’s work is strictly prohibited.

Academic dishonesty:

Cheating is a very serious offense. It will be dealt with in the most severe manner allowable under University regulations. If caught cheating, you can expect a failing grade and initiation of a cheating case in the University system.

Basically, its an insult to the instructor, the department and major program, and most importantly, to the person doing the cheating. Just don't.

If in doubt about what might constitute cheating, send e-mail to your instructor describing the situation. If you notice anyone cheating, please report it to the instructor or the TA. Do not deal with it yourself.

Discrimination:

State and Federal laws as well as Iowa State University policies prohibit any form of discrimination on the basis of race, color, age, religion, national origin, sexual orientation, gender identity, sex, marital status, disability, or status as a U.S. veteran. Language or gestures of discriminatory nature will not be tolerated. Severe cases will be reported to appropriate offices. See ISU policies at http://www.hrs.iastate.edu/hrs/files/reaffirmation.pdf

Let us make every effort to work together and create a positive, collegial, caring, and all-supportive learning environment in our classroom, laboratory, TA office, and instructor office.

Disability accommodation:

Individuals with physical or mental impairments who are otherwise qualified to perform their work or pursue their studies may request reasonable accommodations to enable them to work or continue their studies.

If you believe you have learning disability, you must contact Student Disability Resources at the Academic Success Center to initiate the accommodation process.

Accommodation for religion based conflict:

Iowa State University welcomes diversity of religious beliefs and practices, recognizing the contributions differing experiences and viewpoints can bring to the community. Students with religion based conflict should talk to the instructor and appropriate university offices to request accommodations at the earliest possible time.

 

Fabrication Privilege

         Circuit fabrication is not required for the course

         It is offered free as a privilege

         Requirements for this privilege

o   Detailed simulation results demonstrating that circuit is highly likely to work

o   Sufficient testing plan (what to measure and how)

o   Promise to test (availability and commitment of time)

o   Register in ee599CD in Spring for 1 credit for each op amp and submit a report to MOSIS

         Benefits:

o   Valuable experience

o   Increased marketability

o   Get one credit for fabrication and testing

         Limits: max two submissions per student

 

Relevant Mosis pages:

 

        Main page

        AMI processes

        AMI 0.5 process

        AMI 0.5 Test Data and SPICE model parameters

        Fabrication Schedule for 2007

        Design Rules

       AMI 0.5 T61F Run Test Results

       AMI 0.5 Corner Parameters

         FAQ from comp.lsi.cad

         MOSIS Pads directory.

 

 

Useful Links

o    Cadence (CAD tool) User's Guide

o    SMIrC Laboratory -Publications