EE 501: CMOS Analog Integrated Circuit Design
Degang Chen: 2134 Coover Hall
Office Hour: any time that is convenient to you
Phone: 294-6277; 294-8432(fax);
E-mail: djchen@iastate.edu
Please include "EE501" in the subject line in all email communications to avoid junk-filtering
Teaching Assistant:
Name: Mr. Xu Zhang, PhD student
Voice phone: (515) 708 0589
E-mail: cxzhang@iastate.edu
Office: 3102 Coover
Hall
Office hour: TBA
Lecture Notes and supplemental materials:
·
Course Admin; Intro to Analog IC and
CMOS process
·
CMOS Transistor Models; BSIM4.6.4 Manual; BSIM4.6.5 Bugfix;
·
BSIM Group
Webpage; BSIM4.7.0 Manual, BSIM4.7.0 Enhancement and Bugfix
·
http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ami-c5/v05q_c5n_non_epi-params.txt
·
MOS CS amp;
·
MOS diff amp;
Mason’s formula for TF;
·
CMFB
·
Reference; OrignBG64; WidlarBG71; KuijkBG73;BrokawBG74; BanbaBG99;
·
Low voltage push pull output
·
DC gain and SR enhancement; DC
gain enh EL paper; SRE EL paper;
DC
GE freq response; DCGE
ISCAS; SRE ISCAS;
·
·
·
·
Monticelli;
Huijsing;
Huijsing1; Harrison; Sanchez;
·
·
Layout
·
·
Kumar’s Final Oral Exam Presentation
·
midterm
·
Mason’s Gain Formula for finding
transfer functions
Evaluation components and
weighting in final grades
Final Grade Weighting
•
Laboratory:
15 points
•
Design
projects: 15 points each
•
Homework:
15 points
•
Midterm
Exam: 15 points
•
Final
Exam: 25 points
•
Bonus: up to 5 points
Final Grade Scale:
•
A: 95+
•
A-: 90 –
95
•
B+: 85 –
90
•
B: 80 –
85
•
NR:
<80 as default
•
If a
grade is requested:
–
B-:
75-80
–
C+:
70-75
–
C: 65-70
–
F:
<65
Laboratory
·
Official
required laboratories start in week 2.
·
Lab
0 will be provided for this week
–
Students
with any of the following do not need to do lab 0
•
have
taken ISU EE435
•
have
IC design/layout experience from industry
•
have
taken an IC design course using Cadence
•
have
otherwise had >50 hours using Cadence tools for circuit design and
simulation
–
assignment
will be posted ASAP
–
TA
will be available for help
·
Each
lab is for either one week or two weeks
·
A
lab report is due at the beginning of the next lab
·
Lab
report should be brief, and consists of the following:
–
Briefly
state why you did the lab (purpose)
–
Briefly
describe the main tasks and how you did them (what and how)
–
Briefly
describe the results (with graphs, tables, explanatory captions)
–
Briefly
state what you have learned
–
Additional
comments, problems, doubts, …
·
Lab
report grading
–
One
week labs are worth 10 points
–
Two
week labs are worth 20 points
–
For
each day the report is late, 10% (1 or 2 points) will be deducted.
–
Graded
report will be returned during the lab that is one week after you turned it in.
·
There
will be no lab during the week a project is due, and possibly the week before
or after, but not both.
Homework Assignments:
·
One
assignment every 1 or 2 weeks
·
Each
assignment will have 10 problems.
·
Each
problem is worth 1 point, regardless of level of difficulty
·
Total
number of assignments: 7~8
·
Due
date: one week after it is posted unless otherwise specified
·
Late
HW policy: 1 point penalty for each calendar day it is late.
Design Project Assignments:
·
Project 1; due date: announce in class
·
Project 2; due date:
·
For
each project, the preliminary project report due date will be posted.
·
After
that, students will make presentations about their project.
·
After
the presentation, you will be given time to make updates on your report and
presentation.
·
The
final due date for the presentation and report will be announced at the
presentation time.
·
Penalty
for late submission: 1 point per day for either the preliminary or final
submission.
Catalog Description
E E
501. Analog and Mixed-Signal VLSI
Circuit Design Techniques. (Cross-listed with
Cpr E). (3-3) Cr. 4.
F. Prereq: 435. Design techniques
for analog and mixed-signal VLSI circuits. Amplifiers;
operational amplifiers, transconductance amplifiers,
finite gain amplifiers and current amplifiers. Linear
building blocks; differential amplifiers, current mirrors, references,
cascading and buffering. Performance characterization
of linear integrated circuits; offset, noise, sensitivity and stability.
Layout considerations, simulation, yield and modeling for high-performance
linear integrated circuits.
Course Objectives
Understand fundamental concepts related to sources of non-idealities, matching, noise, nonlinearities, and stability.
Design and analyze key building blocks.
Design and analyze multistage op amps for low voltage, low power, high gain, and high speed applications.
Experience floor planning, analog layout, corner simulation, yield assessment, design for test, and test planning.
Prerequisite courses and
prerequisite topics
The official prerequisite course for EE501 is EE435,
which has EE 330, 324, 332, and either EE
322 or Stat 330 as prerequisite.
In terms of topical contents, the prerequisite for EE501 includes,
ranking from the most important:
• Proficiency and fluency in using Cadence, Synopsis, and other analog IC design and simulation tools (EE330)
• Knowledge of basic amplifier structures, their large signal and small signal analysis, and computation of their gain, bandwidth, impedance and so on. (EE435)
• Knowledge of how transistors work, including various operation regions, large and small signal models, and parasitics models. (EE435, 330, 332)
• Knowledge of signals and systems, including poles, zeros, transfer functions, frequency response, transient response, stability, phase margin, and so on. (EE324, 435)
• Knowledge of semiconductor fabrication processes and how transistors, resistors, capacitors, diodes, etc., are made. (EE332)
• Knowledge of probability, random variables, pdf’s, noise, signal to noise ratio, noise transfer, and so on. (EE322/Stat330)
Fabrication Privilege
•
Circuit fabrication is not required for this course
•
It is offered free as a privilege
•
Requirements for having this privilege
o
Detailed simulation results demonstrating that circuit is highly
likely to work
o
Sufficient testing plan (what to measure and how)
o
Promise to test (availability and commitment of time)
o
Register in ee599CD in Spring for 1 credit for each op amp and
submit a report to MOSIS after chip is tested
•
Benefits:
o
Valuable experience
o
Increased marketability
o
Get one credit for fabrication and testing
•
Limits: max two submissions per student
Other policies
Teamwork, collaboration, and helping each
other:
For tasks intended
for group work, you are expected to find a partner and share the tasks among
the group members. In a group project, effective teamwork is critical to
maximize the productivity of the whole group. In the submitted work, identify
components and indicate percentage contribution by each member to each
component.
For tasks not
intended for group work, individual submission is required. In this case, you
are encouraged to discuss among your friends on how to attack problems.
However, you should write your own solution. Copying other people’s work is
strictly prohibited.
Academic dishonesty:
The class will follow
http://www.dso.iastate.edu/ja/academic/misconduct.html
Cheating is a very
serious offense. If caught cheating, you can expect a failing grade and
initiation of a cheating case in the University system.
Basically, it’s an insult to the instructor, the department and
major program, and most importantly, to the person doing the cheating. Just
don't.
If in doubt about
what might constitute cheating, send e-mail to your instructor describing the
situation. If you notice anyone cheating, please report it to the instructor or
the TA. Do not deal with it yourself.
Disability Accommodation
Iowa State University complies with the Americans with Disabilities Act and Sect 504 of the Rehabilitation Act. If you have a disability and anticipate needing accommodations in this course, please contact (instructor name) to set up a meeting within the first two weeks of the semester or as soon as you become aware of your need. Before meeting with (instructor name), you will need to obtain a SAAR form with recommendations for accommodations from the Disability Resources Office, located in Room 1076 on the main floor of the Student Services Building. Their telephone number is 515-294-7220 or email disabilityresources@iastate.edu . Retroactive requests for accommodations will not be honored.
Dead Week
This class follows the Iowa State University Dead Week policy as noted in section 10.6.4 of the Faculty Handbook http://www.provost.iastate.edu/resources/faculty-handbook .
Harassment
and Discrimination
Iowa
State University strives to maintain our campus as a place of work and study
for faculty, staff, and students that is free of all forms of prohibited
discrimination and harassment based upon race, ethnicity, sex (including sexual
assault), pregnancy, color, religion, national origin, physical or mental
disability, age, marital status, sexual orientation, gender identity, genetic
information, or status as a U.S. veteran. Any student who has concerns about
such behavior should contact his/her instructor, Student Assistance at 515-294-1020 or email dso-sas@iastate.edu, or the Office of Equal Opportunity and
Compliance
at 515-294-7612.
Religious
Accommodation
If
an academic or work requirement conflicts with your religious practices and/or
observances, you may request reasonable accommodations. Your request must be in
writing, and your instructor or supervisor will review the request. You or your instructor may also seek
assistance from the Dean of Students
Office
or the Office of Equal
Opportunity and Compliance.
Contact
Information
If you are experiencing, or
have experienced, a problem with any of the above issues, email academicissues@iastate.edu.