EE 501: CMOS Analog Integrated Circuit Design
Degang Chen: 2134 Coover Hall
Office Hour: any time that is convenient to you
Phone: 294-6277; 294-8432(fax);
E-mail: djchen@iastate.edu
Please include "EE501" in the subject line in all email communications to avoid junk-filtering
Teaching Assistant:
Name: Mr. Hao Meng, PhD student
Voice phone: (515) 708 1212
E-mail: hmeng@iastate.edu
Office: 3102 Coover
Hall
Office hour: TBA
Secondary helper: Mr. Chongli Cai, PhD student
Voice phone: (312) 662 8005
E-mail: chonglic@iastate.edu
Office: 3011 Coover
Hall
Lecture Notes and supplemental materials:
·
Course Admin;
·
CMOS tech;
·
CMOS devices;
·
MOSFET model;
·
Chongli’s
presentation on gm/Id design
·
SwitchesResistorsDiodesSourcesMirrors
·
Widlar; Kuijk;
Brokaw; Banba;
BGReference;
·
Mason’s rule;
·
Compensation;
·
CMFB;
·
Op Amp Test basics; Testing Op Amps and
Comparators;
·
Layout; C.He
Paper, DaiHeISCAS, Application to ADC testing,
·
Op Amp Specs; OPA4316; noise
Analysis;
Evaluation components and
weighting in final grades
Final Grade Weighting
•
Laboratory:
15 points
•
Design
project 1: 15 points
•
Design
project 2: 20 points
•
Homework:
10 points
•
Midterm
Exam: 15 points
•
Final
Exam: 25 points
•
Bonus: up to 5 points for asking
questions, answering questions
•
Post
course bonus: 10 points for each fabricated/tested/working
project
15 points for developing/demonstrating a
publishable tech
Final Grade Scale:
•
A: 95+
•
A-: 90 –
95
•
B+: 85 –
90
•
B: 80 –
85
•
NR: <
80 as default
But if a grade is requested by the student,
the following scale will be used:
* B-: 75-80
* C+: 70-75
* C: 65-70
* F: <65
If
your original grade is NR and you have received post semester bonus, I can
change your grade retroactively.
Laboratory
The TA maintains a lab
webpage, at the address given above. Please check it on a regular basis.
· Official required
laboratories start in week 2 with Lab 1.
· Lab 0 will be provided for the
first week
–
Students
with any of the following do not need to do lab 0
•
have
taken ISU EE435
•
have
IC design/layout experience from industry
•
have
taken an analog IC design/layout course elsewhere using Cadence
•
have
otherwise had > 50 hours using Cadence tools for analog circuit design and
simulation
–
Assignment
will be posted before lab time of week 1.
–
TA
will be available for help
· Each lab is for either one
week or two weeks
· A lab report is due at the
beginning of the next lab
· Lab report should be brief,
and consists of the following:
–
Briefly
state why you did the lab (purpose)
–
Briefly
describe the main tasks and how you did them (what and how)
–
Briefly
describe the results (with graphs, tables, explanatory captions)
–
Briefly
state what you have learned
–
Additional
comments, problems, doubts, …
· Lab report grading
–
Each
lab is worth 10 points
–
For
multi-week labs, the same score will be repeated for all the weeks
–
For
each day the report is late, 1 point will be deducted.
–
Graded
report will be returned during the lab one week after you turned it in.
· There will be no lab during
the week a project is due, and possibly the week before or after, but not both.
· There will be no lab in the
dead week and the final exam week.
Homework Assignments:
· Problems will be assigned
during the lectures or by posting at the webpage
· All problems are due on
Wednesdays after the week they are assigned
· Late HW policy: accepted but
with partial penalty.
·
HW2;
·
HW3;
(Unless
specifically stated otherwise, homework will be assigned during the lecture,
spread out in the lecture slides. All homework problems are due on Wednesday of
the week after it was assigned. For example, if a problem is given today which
is Monday, it is due on next week’s Wednesday. Similarly, if today is Wednesday
and a problem is given in today’s lecture, it is also due on Wednesday of next
week.)
Design Project Assignments:
·
Project 1; due date: announce in class
·
Project 2; due date: announce in class
Design Project Teams:
·
Project
1: you should work in team of two, with a possible one team of 3.
You should form your teams on your own, and notify the TA
and Instructor
·
Project
2: you should work in team of 4, with a maximum of one possible team of 5, or
with a maximum possible 2 teams of 3.
Your project 2 team should contain no
project 1 team members.
If we your teams has 3 members, we can
ask one auditing student to help.
If your team has 5, the instructor will
give you some extra tasks.
Design Project report and presentation:
·
For
each project, the preliminary project report due date will be announce in class.
·
On
that, students will make presentations about their project.
·
All students will also need to submit their ppt
files before any presentation starts.
·
The
order in which students make presentations will be randomly decided.
·
All
students are required to participate in all presentation, either as presenters
or as reviewers.
·
All reviewer students are encouraged to
ask questions to the presenter students.
·
After
the presentation, you will be given time to make updates on your report and
presentation.
·
The
final due date for the presentation ppt and report pdf will be announced at the presentation
time.
·
Penalty
for late submission: 1 point per day for either the preliminary or final
submission.
Catalog Description
E E 501. Analog and
Mixed-Signal VLSI Circuit Design Techniques. (Cross-listed with Cpr E). (3-3) Cr. 4. F. Prereq:
435. Design techniques for analog and mixed-signal VLSI circuits.
Amplifiers; operational amplifiers, trans-conductance amplifiers, finite gain
amplifiers and current amplifiers. Linear building blocks; differential
amplifiers, current mirrors, references, cascading and buffering. Performance
characterization of linear integrated circuits; offset, noise, sensitivity and
stability. Layout considerations, simulation, yield and modeling for
high-performance linear integrated circuits.
Course Objectives
Understand fundamental concepts related to sources of non-idealities, matching, noise, nonlinearities, and stability.
Design and analyze key building blocks.
Design and analyze multistage op amps for low voltage, low power, high gain, and high speed applications.
Experience floor planning, analog layout, corner simulation, yield assessment, design for test, and test planning.
Prerequisite courses and
prerequisite topics
The official prerequisite course for EE501 is EE435,
which has EE 330, 324, 332, and either EE
322 or Stat 330 as prerequisites.
In terms of topical contents, the prerequisite for EE501 includes,
ranking from the most important:
• Proficiency and fluency in using Cadence, Synopsis, and other analog IC design and simulation tools (EE330)
• Knowledge of basic amplifier structures, their large signal and small signal analysis, and computation of their gain, bandwidth, impedance and so on. (EE435)
• Knowledge of how transistors work, including various operation regions, large and small signal models, and parasitics models. (EE435, 330, 332)
• Knowledge of signals and systems, including poles, zeros, transfer functions, frequency response, transient response, stability, phase margin, and so on. (EE324, 435)
• Knowledge of semiconductor fabrication processes and how transistors, resistors, capacitors, diodes, etc., are made. (EE332)
• Knowledge of probability, random variables, pdf’s, noise, signal to noise ratio, noise transfer, and so on. (EE322/Stat330)
Fabrication Privilege
•
Circuit fabrication is not required for this course
•
But you do receive bonus for your EE501 grade
•
It is offered free of charge as a privilege
•
Requirements for having this privilege
o
Detailed simulation results demonstrating that circuit is highly
likely to work
o
Sufficient testing plan (what to measure and how)
o
Promise make PCB to test your op amp (availability and
commitment of time)
o
Register in ee599CD in Spring for 1 credit for each op amp and
submit a report to MOSIS after chip is tested
•
Benefits:
o
Valuable design/simulation/layout/tape out/test experience
o
Increased marketability
o
Get one credit for fabrication and testing
o
Get bonus points for your EE501 grade
•
Limits: max two submissions per student
Other policies
Lab Safety
Safety in the lab is a number one priority
for students and instructors and to ensure a safe laboratory experience, a brief
safety presentation will be given the first day of lab. It is mandatory that
all students attend this presentation. Moreover, it is expected that students
follow any and all posted safety guidelines. For reference, a copy of the
University Laboratory Safety Manual can be found at:
www.ehs.iastate.edu/sites/default/files/uploads/publications/manuals/labsm.pdf
Teamwork, collaboration, and helping each other:
For tasks intended
for group work, you are expected to find a partner and share the tasks among
the group members. In a group project, effective teamwork is critical to
maximize the productivity of the whole group. In the submitted work, identify
components and indicate percentage contribution by each member to each
component.
For tasks not
intended for group work, individual submission is required. In this case, you
are encouraged to discuss among your friends on how to attack problems. However,
you should write your own solution. Copying other people’s work is strictly
prohibited.
Academic dishonesty:
The class will follow Iowa State
University’s policy on academic dishonesty.
Anyone suspected of academic dishonesty will be reported to the Dean of
Students Office.
http://www.dso.iastate.edu/ja/academic/misconduct.html
Cheating is a very
serious offense. If caught cheating, you can expect a failing grade and
initiation of a cheating case in the University system.
Basically, it’s an
insult to the instructor, the department and major program, and most
importantly, to the person doing the cheating. Just don't.
If in doubt about
what might constitute cheating, send e-mail to your instructor describing the
situation. If you notice anyone cheating, please report it to the instructor or
the TA. Do not deal with it yourself.
Disability Accommodation
Iowa State University complies with the Americans with Disabilities Act and Sect 504 of the Rehabilitation Act. If you have a disability and anticipate needing accommodations in this course, please contact (instructor name) to set up a meeting within the first two weeks of the semester or as soon as you become aware of your need. Before meeting with (instructor name), you will need to obtain a SAAR form with recommendations for accommodations from the Disability Resources Office, located in Room 1076 on the main floor of the Student Services Building. Their telephone number is 515-294-7220 or email disabilityresources@iastate.edu . Retroactive requests for accommodations will not be honored.
Dead Week
This class follows the Iowa State University Dead Week policy as noted in section 10.6.4 of the Faculty Handbook http://www.provost.iastate.edu/resources/faculty-handbook .
Harassment
and Discrimination
Iowa
State University strives to maintain our campus as a place of work and study
for faculty, staff, and students that is free of all forms of prohibited
discrimination and harassment based upon race, ethnicity, sex (including sexual
assault), pregnancy, color, religion, national origin, physical or mental
disability, age, marital status, sexual orientation, gender identity, genetic
information, or status as a U.S. veteran. Any student who has concerns about
such behavior should contact his/her instructor, Student Assistance at 515-294-1020 or email dso-sas@iastate.edu, or the Office of Equal Opportunity and Compliance at
515-294-7612.
Religious
Accommodation
If
an academic or work requirement conflicts with your religious practices and/or
observances, you may request reasonable accommodations. Your request must be in
writing, and your instructor or supervisor will review the request. You or your instructor may also seek
assistance from the Dean of Students
Office
or the Office of Equal
Opportunity and Compliance.
Contact
Information
If you are experiencing, or
have experienced, a problem with any of the above issues, email academicissues@iastate.edu.
Useful Web Link:
*
EE330 Webpage: http://class.ece.iastate.edu/ee330/
*
EE435 Webpage: http://class.ece.iastate.edu/djchen/ee435/2013/
*
2011 Lab Webpage: http://home.engineering.iastate.edu/~yulong/EE501lab/ (Cadence User Guide can be found here)
*
NCSU Cadence Design Kit: http://www.eda.ncsu.edu/wiki/NCSU_EDA_Wiki
*
MOSIS wafer electrical test results:
https://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ami-c5/v23r-params.txt
*
MOSIS Scalable CMOS Design Rule: http://www.mosis.com/files/scmos/scmos.pdf
*
ISU VLSI Wiki: http://wikis.ece.iastate.edu/vlsi/index.php/Main_Page
*
Cadence 6.1 Setup: http://wikis.ece.iastate.edu/vlsi/index.php/Cadence_6.1_Setup
*
For IBM 0.13um
process setup: Setup for IBM
*
NX Client: http://www.nomachine.com/download.php
Make sure that you are using NX 3.5, which
could be download from here http://wikis.ece.iastate.edu/downloads/NX/
*
International Technology Roadmap for Semiconductors:
http://www.itrs.net/Links/2011ITRS/Home2011.htm Download the file here.