Spring 2008
Class Time: TR 2:10-3:30, in Pearson 3119
Degang Chen, 329 Durham Center
Office Hour: to be determined, or any other time that I am available
Voice: (515)294-6277, Fax : (515)294-4657
e-mail: djchen@iastate.edu, Please include "EE507" in the subject line in all email communications
Course Description:
This course will have a major emphasis on CMOS VLSI circuits design, that is, CMOS VLSI design for communication circuits and systems. Although our goal is to design circuits for applications conforming to certain communication standards, our coverage of communication theory, protocols, etc. will be limited to the very minimum that is needed for circuit design.
For circuit design, layout, and simulation, we will use Cadence, Synopsis, Matlab, etc. On campus students will have access to all tools needed. For off-campus students, if you have your own CAD and simulation tools, go ahead and use your favorite tools. If you need access to such tools at ISU, make sure you have an ISU login name and password, high speed internet connection, and x-windows. We will talk about remote access to the servers at the beginning of the semester.
Topics involved in the design of communication systems include:
basic components and devices such as varactors, integrated inductors, as well as resistors, MOST, and BJT;
common building blocks such LNAs, mixers, VCOs, phase-frequency detectors, loop filters, charge pumps, frequency dividers, delay lines;
subsystems DLLs and PLLs (loop characteristics, behavioral or mixed-mode simulation, design considerations), phase noise and jitter (time and frequency domain characterization, jitter generation/transfer/tolerance, phase noise and jitter in VCOs and PLLs, jitter measurement and testing), data converters in communications, PLL applications (clock generation/distribution, jitter attenuators, frequency synthesizers, fractional-N synthesizers, clock and data recovery circuits), adaptive filters, equalizer, and transceivers, if time.
Homework and exams:
There will be about 7-10 HW assignments, some are related to paper and pencil work, some related to reading and summarizing papers, and others related to designing and simulating circuits. Handwritten HW solutions are acceptable most of the time, but you are encouraged to submit HW electronically in MSword. For an average student expecting an average grade, I expect you to spend 10 hours a week including attending lectures. If an assignment is taking too much time, please let me know and I'll make adjustments to the assignments.
There will be one midterm exam and one final exam. Both will be open book and open notes. You can consult with papers, books, or internet articles. For the final exam time, check the university home page for schedule of final exams. The time for the midterm exam will be decided in class.
You are encouraged to discuss with each other for HW problems. I'll let you have the email addresses of all of your classmates. It's up to you to find partners if you so choose. However, the exams will be for individual work. You cannot consult with any person other than me for your exams, not your classmates, not your colleagues, not your family members.
Late HW or make-up policy:
No late HW or make-up exams except documented unpredicted emergency situations. For any other reasons, you should contact me before hand to obtain pre-authorization for deviation from the posted due date, or to arrange a different exam time. However the final exam time can not be changed due to university policies.
Grading:
Homework: 1/3
Exams: 1/3
Project: 1/3
Attendance:
Attendance is not required. No attendance will be taken during class.
You are responsible for all course materials, announcements, notes, etc. made during our regular class meeting times.
If you do decide to come to class, prompt arrival to class is appreciated.
If you have to leave early, you should let me know before hand.
While in the classroom, you should be only doing or talking about things related to the class.
Classroom Behavior:
You are encouraged to ask specific questions related to the lecture material as well as more general questions related to the course topics or to the broad engineering profession.
You are encouraged to answer questions that I pose or questions that your classmates ask. Do not be concerned about the correctness of your answers. Your participation can only positively affect your grades.
Please turn off your cell phone before the class. Letting your cell phone ring in the classroom, or answering your phone during class time, or walking out to answer a phone will negatively affect your grade. (Example exception would be: you let me know before class that you are expecting an important call and you put your phone in silent mode.)
All activities prohibited by laws or discouraged by university rules are not allowed in the classroom, such as smoking and alcohol drinking. Snacks and water drinking are OK as long as you do not disturb the class.
Comments that are of racial discrimination, sexual discrimination, religious discrimination, or other hurtful nature are prohibited.
Academic Honesty:
It is the responsibility of the instructor to encourage an environment where you can learn and your accomplishments will be rewarded fairly. Any behavior that compromises the basic rules of academic honesty as described in the General Catalog will not be tolerated.
Americans with Disabilities Policy Statement
The Americans with Disabilities Act (ADA) is a federal anti-discrimination statute that provides comprehensive civil rights protection for persons with disabilities. Among other things, this legislation requires that all students with disabilities be guaranteed a learning environment that provides for reasonable accommodation of their disabilities. If you believe you have a disability requiring an accommodation, please first contact the appropriate university offices for guidance and evaluation and then contact me privately in my office.
Low noise amplifiers; TUe LNA slides; Neihart Paper; Questions
LNA Linearizing Using Bipolar TA&M; LNA high linear; LNA current reuse
Phase noise; Jitter in Ring VCO McNeil; Phase noise Hajimiri
LNA Design Optimization; LNA noise optimization; Shaeffer LNA; Karanicolas LNA
Jitter in Ring Oscillator by McNeill, by Hajimiri and Lee
phase noise in LC oscillator by Huang; Hajimiri and Lee
Text Book: None. Will distribute pdf files for papers and class notes
Unfortunately, there is no one single text book whose contents match what we would like to cover in this course. Class lecture notes will be posted at this web page. The materials of the lecture will be taken from a combination of reference sources listed in the following. You are encouraged to refer to these references for more details than given in the lecture. pdf form of certain non-book articles will be posted as reading materials.
Reference sources for course materials:
B. Razavi, RF Microelectronics, Prentice-Hall PTR, NJ, 1998.
Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 2003.
Bosco H. Leung, VLSI for Wireless Communication, Prentice Hall, 2002.
Lecture notes on RF CMOS IC design from Technical University of Eindhoven.
Lecture notes on frequency synthesizer from GATech
Lecture notes on RF CMOS circuits from ISSCC short course
Lecture notes on wideband communications from ISSCC short course
Desensitized personal notes and circuit examples from industry engineers
Additional References:
Razavi, Phase-locking in High-performance Systems, from Devices to Architecture, Wiley-IEEE, 2003.
Razavi, Monilithis Phase-locked Loops and Clock Recovery Circuits, Theory and Design, Wiley-IEEE, 1996.
J. Crols and M. Steyaert, “CMOS Wireless Transceiver Design,” Boston, Kluwer Academic Pub., 1997.
A. Bensky, “Short-Range Wireless Communications,” 2nd Edition, Elsevier/Newnes, Amsterdam, 2004.
R. Gilmore and L. Besser, “Practical RF Circuit Design for Modern Wireless Systems,” Norwood, Art House, 2003.
J. Rogers, C. Plett, “Radio Frequency Integrated Circuit Design,” Artech House, 2003.
V. L. Rhode, “Microwave and Wireless Synthesizers Theory and Design,” John Wiley & Sons, New York, 1997.
Roland E. Best, Phase-Locked Loops : Design, Simulation, and Applications (Professional Engineering), McGraw-Hill Professional, 5th edition, 2003
Floyd M. Gardner, Phase-lock Techniques, Wiley-Interscience, 2 edition, 1979.
Donald R. Stephens, Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations, Kluwer Academic Publishers, 2nd edition, 2001.
B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.
G. Gonzalez, “Microwave Transistor Amplifiers,” 2nd. Ed., Prentice Hall, 1997.
Allen and Holberg, CMOS Analog Circuit Design, 2nd Edition, Oxford, 2002,
Gray, et al, Analysis and Design of Analog Integrated Circuits, 4th Ed., Wiley, 2001
Hastings, The Art of Analog Layout, Prentice Hall, 2001
William Liu, Mosfet Models for Spice Simulation, Including BSIM3v3 and BSIM4, Wiley-IEEE, 2001
Daniel P. Foty, MOSFET Modeling With SPICE: Principles and Practice, Prentice Hall, 1996
Yannis Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press; 2nd edition (May 1, 2003)
Laker and Sansen, Design of Analog Integrated Circuits, McGraw Hill, 1994
David Johns & Ken Martin , Analog Integrated Circuit Design, John Wiley & Sons, Inc. 1997
Behzad Razavi, Design of Analog CMOS Integrated, CircuitsMcGraw-Hill, 1999Geiger, et al, VLSI Design Techniques for Analog and Digital Circuit, McGraw Hill, 1990
Behavioral and numerical simulation and signal processing tool (Matlab)