1. For each state diagram below, give a corresponding implementation-level state table. Assume that state Si is encoded by using a binary representation of value of i.(a) S0 -> S1 -> S2 -> S3
2. Give a state diagram and an implementation-level state table for a state machine having four state and 1-bit input i, such that if i=1 the machine makes a transition "upwards," i.e., S0 -> S1 -> S2 -> S3 -> S0 and if i=0 the machine makes a transition "downwards," i,e, S0 -> S3 -> S2 -> S1 -> S0.3. Design a circuit, in the form of next state equations in canonical sum-of-products form (and simplify them if you like), that will implement the following state machine.
Current Input Next X Y I X Y 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 1 1 1 0 1 0 1 1 1 0 0 4. Given the state machine in the above table, indicate for each input sequence below, the state the machine is in after the last digit has been read in. Assume the digits are read in from right to left
(a) 1110001100
(b) 111111
(c) 513 1s (1 is repeated 513 times)
(d) 11101111110011000000
(e) 555 1s followed by 234 0s