1. Objectives
In this lab you will also gain practical experience with designing devices by treating them as Finite State Machines. You will also continue to practice simplifying logic expressions and programming circuits in the Quartus ii design environment.
1.1 Reference Files for Lab
2. Prelab
Information for this lab can be found in Chapter 8, in particular sections 8.7.1 – 8.7.3, of your text: “Fundamentals of Digital Logic with Verilog Design” by Brown and Vranesic. You may also be able to refer to your lecture notes. Please complete the answer sheet for each step of the lab, and make sure you have your designs and circuit diagrams ready before the lab session. Please read the lab instructions as they will help you to complete this pre-lab.
For this lab step you are to design, build and simulate a device that just cycles through six states. It will have no inputs (except the clock) and no outputs (that is to say there is no output associated with each state, however, the circuit should still output the current state). The device is a modulo-6 counter. The design method will be similar to that for the modulo-8 counter in Section 8.7 of Vranesic and Brown, except that there will be fewer states, there is no w input, and there will be no outputs.
To complete this step, fill in the information on the answer sheet for step 1. When you have filled in the answer sheet, you will be ready to build and simulate this sequential circuit.
Use D flip-flops for memory. As in Lab 13a, you should use the dff symbol from the prim library to create your D flip-flops. You are to compile the file, use the waveform editor to prepare the file for simulation, and then simulate the design using the simulator. Does your device require Asynchronous Reset (CLRN) on the flip-flops? Why, or why not? When you are convinced your design is working correctly, verify your observations and design with your TA.
You will now design a more complex sequential device. Again, modeling this device as a Finite State Machine, create a counter that repeatedly counts 0, 2, 4, 5, 0, 2, 4, 5, 0, 2... . This device will have outputs that will be labeled L[2..0].
Fill in the necessary FSM information in the answer sheet, design the device, and save this design. Use the D flip-flop for your device’s memory.
Simulate the circuit and observe the behavior of this counter. When you are confident that you understand the behavior of this device, and are convinced that it is performing as predicted, show your work to your TA.
For Step 3, you will build an Up/Down Counter using a FSM model. This counter will count up (0, 1, 2, 3) if the input is a 0, and count down (0, 3, 2, 1) if the input is a 1. In both cases, the counter will continuously cycle through the count.
Complete the information for Step 3 on the answer sheet. Use D flip-flop to provide the device with memory.
Simulate the circuit and observe the behavior of this counter. When you are confident that you understand the behavior of this device, and are convinced that it is performing as predicted, show your work to your TA.