Some of the ongoing activities are summarized below:
The major emphasis on our data converter research is on pipelined structures. Specific interests include methods for minimizing power, self-calibration approaches, strategies for design at very low voltages, built-in self test, synthesis, and design for soft yield targets.
The major emphasis on this project is on layout strategies for enhancing INL and on digital correction algorithms to compensate for inherent nonlinearities in the DAC.
This project focuses on designing amplifiers that exhibit very fast settling. Applications of these structures are focused towards high-speed sample and holds and towards interstage amplifiers in high speed pipelined data converters. One initiative concentrates on optimizing the settling performance for known architectures for a given load capacitance and a fixed power dissipation. A second is directed towards alternative compensation schemes which involve addition of left half-plane zeros and on managing the pole-zero dipoles inherent in such structures. A third is focused at using open-loop or low-gain amplifier structures that exhibit favorable bandwidth properties. A fourth focuses on identifying architectures that offer adequate gain and bandwidth to be useful in sub-100nm technologies. In the latter initiative, several open-loop positive feedback strategies are being investigated.
This project is focused on developing a WEB-based design tool that supports both the design and optimization of electronic circuits. Using JAVA-based applets, the design tool runs on the clients computing platform thus providing for essentially unlimited parallel usage. The tool is structured so that design knowledge from an experienced designer can be captured in the mathematical formulation that characterizes each design in the data repository.
This project focuses on enhancing the matching performance of current mirrors and reducing the offset voltages in differential amplifiers. One initiative in this project concentrates on using non-conventional geometries for current mirrors and differential amplifiers. A second is directed at understanding the effects of parameter gradients through the active region of MOS transistors on the performance of mirrors and differential amplifiers. In support of both initiatives, a simulator is under development that can simulate the lateral dimensional affects of changes in process parameters such as threshold voltage, mobility and gate oxide capacitance density throughout the gate area of the MOS transistors. A third focuses on layout strategies that maximize soft yield for a given area constraint
This project concentrates on serial transceivers that operate at data rates between 200 Mbit/sec to 10 Gbit/sec and beyond. Integral to these initiatives are projects on the design of phase/frequency detectors that operate at the specified data rates, on VCO design, and on the design of PLLs that are integral to these transceivers. A recent initiative that concentrates on jitter modeling of VCOs and PLLs has been initiated.
This project is focused on designing adaptive equalizers in standard CMOS processes that can be used for equalizing the signal coming out of a lossy channel. Emphasis is on channels with data rates between 50 Mbit/sec and 5 Gbit/sec.
This project focuses on the design of high-speed VCOs that are inherently insensitive to process and temperature variations. With this insensitivity, a very low sensitivity of the oscillation frequency to the control voltage can be achieved. This low sensitivity should reduce jitter when these VCOs are used in a PLL-based data recovery system.
This project concentrates on using a DLL rather than a PLL for data recovery in tight-tolerance serial data communication systems. The technique shows promise for reducing the sensitivity to jitter in the incoming signal, for eliminating the jitter associated with the PLL in a conventional structure, and for reducing the time needed by existing PLL-based techniques to acquire lock onto the incoming data.
This project is concentrating on both the thermal noise and 1/f noise in MOS devices. The initiative on the thermal noise issue is directed at establishing consistency between the triode-region and saturation region thermal noise models for the devices. The 1/f focus is also concerned about the consistency in models between the two regions of operation in addition to l the effects of the "birds beaking" region on the overall 1/f noise performance of a device.
We have an emerging project that is directed towards analog and mixed-signal testing and specifically on the inclusion of special purpose built-in self-test (BIST) structures for a useful class of linear and mixed-signal circuits. Initial focus will be on self-testing of Nyquist rate data converters and on the dual-use of self-testing circuitry for both testing and yield enhancement through self-calibration.
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Questions or comments may be sent to Dr. Randall Geiger.