EE/CprE 434
Introduction to Integrated Circuit Design

Fall 2006

Instructor: Prof. Randy Geiger

Syllabus and policies

Page map

| Lecture notes  |  Homework Assignments  |  Exams  |  Lab Handouts |
| Reference material  |  Additional Reading  |

Lecture notes

• Week 01 ( Lecture 01, Lecture 02, Lecture 03 )
• Week 02 ( Lecture 04, Lecture 05, Lecture 06 )
• Week 03 ( Holiday, Lecture 07, Lecture 08 )
• Week 04 ( Lecture 09, Lecture 10, Lecture 11 ) (Reference: CMOS process flow)
• Week 05 ( Lecture 12, Lecture 13, Lecture 14 )
• Week 06 ( Lecture 15, Lecture 16 , Lecture 17
• Week 07 ( Lecture 18p, Lecture 19, Lecture 20p )
• Week 08 ( Lecture 21, Lecture 22, Lecture 23p )
• Week 09 ( Lecture 24 Lecture 25 , Lecture 25 sup , Lecture 26 )
• Week 10 ( Lecture 27, Lecture 28, Lecture 29 )
• Week 11 ( Lecture 30, Lecture 31, Lecture 32 )
• Week 12 ( Lecture 33, Lecture 34, Lecture 35 )
• Week 13 ( Lecture 36, Lecture 37, Lecture 38

　

• Week 14 ( Lecture 39, Lecture 40, Lecture 41 - Exam 2 )
• Week 15 ( Lecture 42, Lecture 43, Lecture 44 )

Homework Assignments

• Homework 1: Assignment, Solution
• Homework 2: Assignment, Solution
• Homework 3: Assignment, Solution
• Homework 4: Assignment, Solution
• Homework 5: Assignment, Solution
• Homework 6: Assignment, Solution
• Homework 7: Assignment, Later
• Homework 8: ,
• Homework 9: ,

Exams

• Exam 1
• Exam 2
• Final Exam

Old exams

• Exam 1: Fall 2002, Fall 2003, Fall 2004, Fall 2005
• Exam 2: Fall 2001, Fall 2002, Fall 2003, Fall 2004, Fall 2005
• Final Exam: Fall 2001, Fall 2002, Fall 2003, Fall 2004, Fall 2005

Lab Handouts

• Lab 1: Pre-lab,  Introduction to an Integrated CAD Tool Environment

• Lab 2: Basic Boolean Circuits

• Lab 3: Layout and LVS (Layout vs. Schematic)

• Lab 4: From Boolean equation to Silicon, Pre-lab for week 2, Submission Guidelines

• Lab 5: Bonding pads

• Lab 6: Models for MOS devices

• Lab 7: Practical issues in Integrated Circuit Layout and Fabrication

• Lab 8: Design and simulation of digital circuits using Hardware Description Languages

• Lab 9: Place-and-Route with SOC Encounter

• Lab 10: Digital system Synthesis Using Synopsys Design Analyzer

• Final Project: Projects, Teams, Presentation Schedule

  • Project 1: Behavioral opamp, Complete opamp (use the command 'tar zxvf opampee434.tar.gz" to extract)

  • All projects: Directions for running post-layout simulations

Reference material

• Complete CMOS process flow (PowerPoint file)

• MOSIS scalable CMOS design rules (PDF)

• MOSIS rules pictorial (All rules in one PDF files)

Some material for final project

•  Verilog tutorial (old lab handout)

• Synopsys tutorial (including which constructs are not synthesizable) (old lab handout)

Lecture notes from Fall 2005

• Week 01 ( Lecture 01, Lecture 02, Lecture 03 )
• Week 02 ( Lecture 04, Lecture 05, Lecture 06 )
• Week 03 ( Lecture 07, Lecture 08 )
• Week 04 ( Lecture 09, Lecture 10, Lecture 11 ) (Reference: Complete CMOS process flow)
• Week 05 ( Lecture 12: a) Diode, Capacitor, MOSFET b) BJT Process Flow c) Device Modeling, Lecture 13, Lecture 14 )
  • Lecture Videos: Video 1, Video 2, Video 3
• Week 06 ( Lecture 15, Lecture 16 , Exam 1) (MOSFET Modeling papers, T56h run parameters)
• Week 07 ( Lecture 18, Lecture 19, Lecture 20 )
• Week 08 ( Lecture 21, Lecture 22, Lecture 23 )
  • Lecture Videos for Lecture 23: Video 1 (watch from 4:04 to 44:44), Video 2 (watch from 30:42 to 45:50)
• Week 09 ( Lecture 24, Lecture 25, Lecture 26 )
• Week 10 ( Lecture 27, Lecture 28, Lecture 29 )
• Week 11 ( Lecture 30, Lecture 31, Lecture 32 )
• Week 12 ( Lecture 33, Lecture 34, Lecture 35 )
  • Lecture Videos.
        Lecture 33: Video.
        Lecture 34: Video 1 (watch from 38:00 to 54:52), Video 2 (watch from 0:55 to 35:58)
• Week 13 ( Lecture 36, Lecture 37, Lecture 38, Lecture 38 High Frequency MOSFET model )
• Week 14 ( Lecture 39, Lecture 40, Lecture 41 )
• Week 15 ( Lecture 42, Lecture 43, Lecture 44 )

Additional Reading

•  VLSI Design Techniques for Analog and Digital Circuits, Geiger/Allen/Strader

Useful Links